NUMERICAL-ANALYSIS OF SHORT-CIRCUIT SAFE OPERATING AREA FOR P-CHANNEL AND N-CHANNEL IGBTS

被引：42
作者：
IWAMURO, N
OKAMOTO, A
TAGAMI, S
MOTOYAMA, H
机构：
[1] FUJI ELECT CO LTD,MATSUMOTO 390,JAPAN
[2] FUJIFACOM CORP,KAWASAKI 210,JAPAN
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 1991年 / 38卷 / 02期
关键词：
D O I：
10.1109/16.69910
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The mechanisms of destructive failure of insulated gate bipolar transistor (IGBT) at short-circuit state are discussed. Results from a two-dimensional numerical simulation of p-channel and n-channel IGBT's are presented. It is found that there are two types of destructive failure mechanisms, which are a secondary breakdown and a latchup. It depends on an absolute value of forward voltage \V(CE)\ which type is dominant in p-channel and n-channel IGBT's. At moderately low \V(CE)\, p-channel IGBT is destroyed by secondary breakdown, and n-channel IGBT, by latchup. These are due to the difference of a type of flowing carrier crossing a base-collector junction of wide base transistor and ionization rates of electrons and holes.
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页码：303 / 309
页数：7
相关论文
共 13 条
[1]   ACCURATE CALCULATIONS OF FORWARD DROP AND POWER DISSIPATION IN THYRISTORS [J].
ADLER, MS .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1978, 25 (01) :16-22
[2]  
Baliga B. J., 1988, International Electron Devices Meeting. Technical Digest (IEEE Cat. No.88CH2528-8), P809, DOI 10.1109/IEDM.1988.32934
[3]  
Baliga B. J., 1982, International Electron Devices Meeting. Technical Digest, P264
[4]   CARRIER MOBILITIES IN SILICON EMPIRICALLY RELATED TO DOPING AND FIELD [J].
CAUGHEY, DM ;
THOMAS, RE .
PROCEEDINGS OF THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, 1967, 55 (12) :2192-+
[5]  
Chang M. F., 1984, International Electron Devices Meeting. Technical Digest (Cat. No. 84CH2099-0), P278
[6]  
KURATA M, NUMERICAL ANAL SEMIC
[7]  
Nakagawa A., 1985, International Electron Devices Meeting. Technical Digest (Cat. No. 85CH2252-5), P150
[8]   SAFE OPERATING AREA FOR 1200-V NONLATCHUP BIPOLAR-MODE MOSFETS [J].
NAKAGAWA, A ;
YAMAGUCHI, Y ;
WATANABE, K ;
OHASHI, H .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (02) :351-355
[9]   NUMERICAL-ANALYSIS ON ABNORMAL THYRISTOR FORWARD VOLTAGE INCREASE DUE TO HEAVY DOPING IN GATED P-BASE LAYER [J].
NAKAGAWA, A .
SOLID-STATE ELECTRONICS, 1981, 24 (05) :455-459
[10]   THE COMFET - A NEW HIGH CONDUCTANCE MOS-GATED DEVICE [J].
RUSSELL, JP ;
GOODMAN, AM ;
GOODMAN, LA ;
NEILSON, JM .
IEEE ELECTRON DEVICE LETTERS, 1983, 4 (03) :63-65
12