A LAYOUT-DRIVEN YIELD PREDICTOR AND FAULT GENERATOR FOR VLSI

被引：17

作者：

DALAL, AR ^{[1
]}

FRANZON, PD ^{[1
]}

LORENZETTI, MJ ^{[1
]}

机构：

[1] N CAROLINA STATE UNIV,DEPT ELECT & COMP ENGN,RALEIGH,NC 27695

来源：

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING | 1993年 / 6卷 / 01期

关键词：

Computer aided design - Crystal defects - Electric fault location - Integrated circuit layout - Integrated circuit manufacture - Integrated circuit testing - Mathematical models - Monte Carlo methods - Probability;

D O I：

10.1109/66.210661

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

IC faults arise from manufacturing defects. Layout analysis is required to determine the yield that is limited by these defects and the probability-graded fault lists that can be used to determine the optimal testing sequence. This requires 1) Accurate analytical expressions relating layout geometries to likelihood of opens and shorts appearing during fabrication, and 2) efficient CAD methods to extract these geometries from the layout. This paper describes all these aspects as implemented in one unified CAD tool. Accuracy is enhanced through the addition of edge information and the validation of shorting defects

引用

页码：77 / 82

页数：6

共 17 条

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[2]

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[4]

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[5]

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[6]

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[7]

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[9]

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[10]

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