Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach

Spin-transfer torque random access memory (STT-RAM) is a promising candidate for universal memory due to its speed, scalability, and non-volatility. A wide range of write speeds from Ito 100 Ds have been reported for STT-RAM. As the storage element of an STT-RAM cell, the switching current of magnetic tunnel junction (MTJ) is inversely proportional to the write pulse width. In this work, we propose a methodology to design STT-RAM for different optimization goals such as read performance, write performance, and write energy by leveraging the trade-off between write current and write time of MTJ. To enable STT-RAM design in advanced technology nodes beyond 22 nm, we model perpendicular MTJ (PMTJ) as the storage element and Fin FET as the access transistor. Our study shows that reducing write pulse width will harm read latency and energy. It is observed that "sweet spots" of write pulse width which minimize the write energy or write latency of an STT-RAM macro may exist. The optimal write pulse width depends on both the device and the architecture specifications. The impact of process variations including the MTJ and the FinFET access transistor are also analyzed.