SYSTOLIC ARRAY ARCHITECTURE IMPLEMENTATION OF PARASITIC-INSENSITIVE SWITCHED-CAPACITOR FILTERS

被引:1
作者
RAUT, R
BHATTACHARYYA, BB
FARUQUE, SM
机构
[1] Concordia Univ, Montreal, Que
来源
IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS | 1992年 / 139卷 / 03期
关键词
FILTERS (SWITCHED-CAPACITOR); SYSTOLIC ARRAY ARCHITECTURE;
D O I
10.1049/ip-g-2.1992.0062
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A systematic procedure is developed for implementing switched-capacitor filters in systolic array architecture. The most complete signal flow graphs that satisfy the conditions of a systolic array, and also the general first- and second-order transfer functions, are considered. A step-by-step reduction procedure is then developed for the second-order signal flow graphs that yield structures which can be implemented with a minimal amount of hardware in LSI/VLSI technology. Implementation of switched-capacitor filters using these reduced signal flow graphs is discussed. Some structures that are not strictly systolic are also considered for second-order filters. Generation of parasitic-insensitive second-order switched-capacitor filters using systolic array architecture are, however, treated in detail, both for biphase (two-phase) and for four-phase clocking schemes. Guidelines for minimising the total capacitance are given and the sensitivity characteristics are provided. Systolic array architecture realisation of a higher-order switched-capacitor filter is illustrated. Results obtained from a bandpass switched-capacitor filter, implemented on a VLSI workstation (SUN) supporting a 3-mu-m CMOS technology, are reported. Simulation results for a fourth-order filter realised using systolic array architecture are provided.
引用
收藏
页码:384 / 394
页数:11
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