A TESTABLE DESIGN OF ITERATIVE LOGIC-ARRAYS

被引：9

作者：

PARTHASARATHY, R ^{[1
]}

REDDY, SM ^{[1
]}

机构：

[1] UNIV IOWA,DEPT ELECT & COMP ENGN,IOWA CITY,IA 52242

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS | 1981年 / 28卷 / 11期

关键词：

D O I：

10.1109/TCS.1981.1084934

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1037 / 1045

页数：9

共 11 条

[1]

DIAS FJO, 1976, IEEE T COMPUT, V25, P605, DOI 10.1109/TC.1976.1674660

[2]

Friedman A.D., 1971, FAULT DETECTION DIGI

[3] EASILY TESTABLE ITERATIVE SYSTEMS [J].

FRIEDMAN, AD .

[4]

FRIEDMAN AD, 1971, THEORY MACHINES COMP

[5]

GRAY FG, 1978, IEEE T COMPUT, V27, P1206, DOI 10.1109/TC.1978.1675029

[6]

KAUTZ WH, 1967, 8TH P S SWITCH AUT T, P161

[7] FAULT DETECTION IN ITERATIVE LOGIC ARRAYS [J].

MENON, PR ;

FRIEDMAN, AD .

[8]

PARTHASARATHY R, 1979, 17TH ANN ALL C COMM

[9] MULTIPLE FAULT DETECTION IN ARRAYS OF COMBINATIONAL CELLS [J].

PRASAD, BA ;

GRAY, FG .

[10]

REDDY SG, UNPUBLISHED