GLOBAL FLOW OPTIMIZATION IN AUTOMATIC LOGIC DESIGN

被引：19

作者：

BERMAN, CL ^{[1
]}

TREVILLYAN, LH ^{[1
]}

机构：

[1] IBM CORP,THOMAS J WATSON RES CTR,DEPT COMP SCI,YORKTOWN HTS,NY 10598

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1991年 / 10卷 / 05期

关键词：

D O I：

10.1109/43.79493

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new method for optimizing digital logic networks is described. Techniques of data flow analysis are used to summarize a circuit efficiently; this summary is used to characterize a class of circuits which are equivalent to the given circuit, and an algorithm is described which reduces the problem of finding small circuits in this equivalence class to the problem of finding a min-cut in an associated graph. This algorithm has been implemented and forms part of an automatic design system in use within IBM. We describe the results of experiments undertaken to evaluate the effect of our new techniques.

引用

页码：557 / 564

页数：8

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