An Efficient Implementation of H.264/AVC Integer Motion Estimation Algorithm on Coarse-grained Reconfigurable Computing System

Variable block size integer motion estimation (VBS-IME) is one of several tools which contribute to H.264/AVC's excellent coding efficiency. However, its high computational complexity and huge memory access bandwidth make it difficult to implement. Therefore, a hardware accelerator is indispensable for full-search VBS-IME in real-time video encoding applications. To overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices in the field of multimedia and communication baseband processing, we have proposed a coarse-grained dynamically reconfigurable computing system, called REMUS. The paper presents architecture and compiling flow proposed for REMUS system, and shows that it is possible to implement a high complexity application as H.264/AVC full-search VBS-IME algorithm with competitive performance on platform of REMUS system. Experimental results have proven that the REMUS system operating at 200 MHz can perform VBSIME at real-time speed for CIF/SDTV@30fps video sequences with two reference frames and maximum search range of [-16,15]/[-8,7]. The implementation, therefore, can apply for H.264/AVC encoder in mobile multimedia applications. REMUS system is designed and synthesized by using TSMC 65nm low power technology. The die size of REMUS is 23.7 mm(2). REMUS consumes about 194mW while working at 200MHz.