A SUBMICROMETER MEGABIT DRAM PROCESS TECHNOLOGY USING TRENCH CAPACITORS

被引:2
作者
NAKAJIMA, S
MINEGISHI, K
MIURA, K
MORIE, T
KIMIZUKA, M
MANO, T
机构
关键词
D O I
10.1109/JSSC.1985.1052285
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
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页码:130 / 136
页数:7
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共 20 条
[1]  
AMAZAWA T, 1983, 15TH C SOL STAT DEV, P229
[2]  
AMAZAWA T, 1984, 16TH C SOL STAT DEV
[3]  
ASAKAWA H, 1982, S VLSI TECH, P88
[4]  
CHWANG R, 1983, ISSCC, P56
[5]   DESIGN OF ION-IMPLANTED MOSFETS WITH VERY SMALL PHYSICAL DIMENSIONS [J].
DENNARD, RH ;
GAENSSLEN, FH ;
YU, HN ;
RIDEOUT, VL ;
BASSOUS, E ;
LEBLANC, AR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (05) :256-268
[6]  
FU SW, 1982, IEDM, P632
[7]  
KIMIZUKA M, UNPUB J VAC SCI
[8]   CIRCUIT TECHNIQUES FOR A VLSI MEMORY [J].
MANO, T ;
YAMADA, J ;
INOUE, J ;
NAKAJIMA, S .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (05) :463-470
[9]   THE OXIDATION OF SHAPED SILICON SURFACES [J].
MARCUS, RB ;
SHENG, TT .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1982, 129 (06) :1278-1282
[10]  
Matsuda T., 1982, International Electron Devices Meeting. Technical Digest, P407