HIGH-SPEED REGENERATOR-SECTION TERMINATING LSI OPERATING UP TO 2.5GBIT/S USING 0.5-MU-M SI BIPOLAR STANDARD-CELL TECHNOLOGY

被引：5

作者：

KAWAI, K

KOIKE, K

ICHINO, H

KOBAYASHI, Y

机构：

[1] NTT LSI Laboratories, Atsugi-shi, Kanagawa. 243- 01, 3-1, Morinosato Wakamiya

来源：

ELECTRONICS LETTERS | 1995年 / 31卷 / 10期

关键词：

SYNCHRONOUS DIGITAL HIERARCHY; BIPOLAR INTEGRATED CIRCUITS; LARGE SCALE INTEGRATION;

D O I：

10.1049/el:19950528

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 2.5 Gbit/s 5.6 Kgate LSI for the STM-64 regenerator-section terminator was fabricated using bipolar standard-cell technology for gigabit per second operation. The technology features high performance cell design and LSI layout design based on an accurate timing analysis. The LSI achieves twice the bit rate and half the power dissipation of reported LSIs.

引用

页码：791 / 792

页数：2

共 7 条

[1]

HARADA I, 1994, ACM IEEE D, P177

[2]

KAWAI K, 1993, 1993 P IEICE FALL A, V57

[3]

KOIKE K, 1993, 1993 P IEEE BIP CIRC, P236

[4]

TAKEI Y, 1993, 1993 P INF PROC SOC, P45

[5] HIGH-SPEED REGENERATOR SECTION TERMINATING LSIS [J].

YAMABAYASHI, Y ;

SATO, Y ;

MATSUOKA, S ;

HOHKAWA, K .

ELECTRONICS LETTERS, 1993, 29 (23) :2057-2058

[6] LINE TERMINATING MULTIPLEXERS FOR SDH OPTICAL NETWORKS [J].

YAMABAYASHI, Y ;

MATSUOKA, S ;

UEMATSU, Y ;

HOHKAWA, K ;

OHHATA, M .

JOURNAL OF LIGHTWAVE TECHNOLOGY, 1993, 11 (5-6) :875-881

[7]

YAMAGUCHI C, 1993, 1993 BIP CIRC TECHN, P63

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