In this paper we analyse the efficiency of an implementation of the discrete wavelet transform using a modified transform domain approach on several classes of DSP and RISC processors. The recently emerged discrete wavelet transform is faster than a standard Fast Fourier Transform, yet it is computationally intensive since the number of computations required increases with the number of octaves. A computationally efficient transform domain implementation of the discrete wavelet transform for wavelets of length 20 or greater is described in this paper. To compare the efficiency of RISC and DSP processors for this method, we first analyse the implementation of a radix 2, radix 4, and split radix Fast Fourier Transform algorithm on some of the latest DSP and RISC processors. This is followed by an analysis of the implementation of complex multiplication on the processors under considerations. We show that both DSP and RISC processors need the same number of instruction cycles to execute a complex multiplication. Finally, we show that those RISC processors which have their instruction cycle time equal to 85% of a DSP processor's instruction cycle time, give better performance than DSP processors for implementing the wavelet transform using a longer wavelet. © 1993 Academic Press. All rights reserved.
