A TIME-BASED MODEL FOR INVESTIGATING PARALLEL LOGIC-LEVEL SIMULATION

In this paper we present a model for studying the effects of timing models and synchronization strategies for event-driven parallel logic-level simulation. We investigate two timing models, variable-delay and unit-delay, and two synchronization strategies, synchronous, and conservative asynchronous. We compare the average parallelism of circuits using the two timing models, and also consider the execution times of circuits using various timing models and synchronization strategies. We show that the circuit parallelism using unit-delay timing provides an upper bound on that of any timebase used in variable-delay timing. We also show that with either timing model, the execution time of the conservative asynchronous strategy is a lower bound over the synchronous strategy, assuming an unlimited number of processors. However, assuming that all events take the same amount of time, we show that with unit-delay timing, the execution time of the synchronous strategy equals that of the asynchronous strategy.