Digital post-calibration of a 5-bit 1.25 GS/s flash ADC

We report a high-speed flash analog to digital converter (ADC) linearization technique employing the inverse Volterra model and digital post processing. First, a 1.25 GS/s 5-bit flash ADC is designed using a 0.18 mu m CMOS, and the signal is quantized by a distributed track-and-hold circuit. Second, based on the Volterra series, a proposed digital post-calibration model is introduced. Then, the model is applied to estimate and compensate the nonlinearity of the high-speed flash ADC. Simulation results indicate that the distortion is reduced effectively. Specifically, the ADC achieves gains of 4.83 effective bits for a 117.1 MHz frequency input and 4.74 effective bits for a Nyquist input at 1.25 GS/s.