ASTRA - AN ASSOCIATIVE RISC-ARCHITECTURE

This paper describes the architecture of a RISC processor which can be used especially for the implementation of various associative processing systems. The processor includes the significant components of a modern microprocessor for a single processor architecture and also some new architectural concepts, especially to support co-processor and multiprocessor architectures. The processor can be used in a monoprocessor architecture as a stand alone associative processor, as a controller for the design of associative processors with word or flag oriented CAM's, and with neural networks. Those memory systems can work as active or passive co-processors. The processor supports the realisation of new associative multiprocessor architectures or known architectures (e.g. PEPE, ASP, etc.) but with extended features. Especially the implementation of serial I/O ports allows the realisation of multidimensional associative architectures. Such associative processor systems are suitable perfectly well for applications in the field of AI, CAD, pattern recognition, etc. © 1989.