A HIGH-SPEED LOW-POWER JFET PULL-DOWN ECL CIRCUIT

An active pull-down output stage that utilizes a "free" JFET available in any n-p-n bipolar technology, applied to a high-speed low-power ECL circuit, is described. Simulation results based on a 0.8-mu-m, double poly-Si, self-aligned bipolar technology indicate that the circuit with a typical loading at a power consumption of 1 mW per gate offers 24% improvement in the pull-down delay and 53% improvement in the load driving capability compared with the conventional ECL circuit.