MULTILEVEL METAL CAPACITANCE MODELS FOR CAD DESIGN SYNTHESIS SYSTEMS

被引：118

作者：

CHERN, JH ^{[1
]}

HUANG, J ^{[1
]}

ARLEDGE, L ^{[1
]}

LI, PC ^{[1
]}

PING, Y ^{[1
]}

机构：

[1] UNIV ILLINOIS, COORDINATED SCI LAB, URBANA, IL 61801 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 1992年 / 13卷 / 01期

关键词：

D O I：

10.1109/55.144942

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new empirical model for multilevel interconnect capacitance is presented. This is the first model that allows designers to compute capacitances of arbitrary complex metal geometries. Such flexibility is achieved by a novel strategy of constructing complex geometries from simple primitive cells. Agreement with accurate simulations and measurements is within 8% over an extensive range of dimensions.

引用

页码：32 / 34

页数：3

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