A REALISTIC FAULT MODEL AND TEST ALGORITHMS FOR STATIC RANDOM-ACCESS MEMORIES

被引：128
作者：
DEKKER, R [1 ]
BEENKER, F [1 ]
THIJSSEN, L [1 ]
机构：
[1] DELFT UNIV TECHNOL,DEPT ELECT ENGN,DELFT,NETHERLANDS
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1990年 / 9卷 / 06期
关键词：
Data Storage; Semiconductor--Storage Devices - Electronic Circuits; Digital--Failure - Failure Analysis - Integrated Circuits; Digital--Computer Aided Design;
D O I：
10.1109/43.55188
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Testing static random access memories (SRAMs) for all possible failures is not feasible and one must restrict the class of faults to be considered. This restricted class is called a fault model. A fault model for SRAMs based on physical spot defects, which are modeled as local disturbances in the layout of the SRAM, is presented. Two linear test algorithms that cover 100% of the faults under the fault model are proposed. A general solution is given for testing word-oriented SRAMs. The practical validity of the fault model and the two test algorithms are verified by a large number of actual wafer tests and device failure analyses.
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收藏
页码：567 / 572
页数：6
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