DESIGN AND TEST OF AN INTEGRATED CRYPTOCHIP

被引：12

作者：

HAFNER, K ^{[1
]}

RITTER, HC ^{[1
]}

SCHWAIR, TM ^{[1
]}

WALLSTAB, S ^{[1
]}

DEPPERMANN, M ^{[1
]}

GESSNER, J ^{[1
]}

KOESTERS, S ^{[1
]}

MOELLER, WD ^{[1
]}

SANDWEG, G ^{[1
]}

机构：

[1] SIEMENS AG,ZFE IS SYS 21,POB 830953,W-8000 MUNICH 83,GERMANY

来源：

IEEE DESIGN & TEST OF COMPUTERS | 1991年 / 8卷 / 04期

关键词：

D O I：

10.1109/54.107201

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The authors describe a self-testing cryptographic coprocessing chip that provides high security for any data protected through its use. Detailed design and test methods and solutions are given, and the design team explains how the new chip's design interacts well in networks and with secure hard disks.

引用

页码：6 / 17

页数：12

共 10 条

[1] ABRAMSON J, 1979, P INT TEST C, P18
[2] [Anonymous], [No title captured]
[3] BARDELL P, 1987, BUILT IN TEST VLSI P
[4] ERCEGOVAC MD, 1985, DIGITAL SYSTEMS HARD
[5] GELSINGER PP, 1987, IEEE DESIGN TEST JUN, P42
[6] KOENEMANN B, 1979, P INT TEST C, P37
[7] MARINESCU M, 1982, P INT TEST C, P236
[8] Ohletz M. J., 1987, Proceedings of VLSI and Computers. First International Conference on Computer Technology, Systems and Applications. COMPEURO 87 (Cat. No.87CH2417-4), P358
[9] RITTER H, 1991, P EUROPEAN TEST C, P53
[10] SCHWAIR TM, 1990, PROCEEDINGS : INTERNATIONAL TEST CONFERENCE 1990, P886, DOI 10.1109/TEST.1990.114107

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