FAULT MODELING FOR DIGITAL MOS INTEGRATED-CIRCUITS

被引：22
作者：
HAYES, JP
机构：
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1984年 / 3卷 / 03期
关键词：
D O I：
10.1109/TCAD.1984.1270076
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：200 / 208
页数：9
相关论文
共 15 条
[1]  
Breuer M. A., 1976, DIAGNOSIS RELIABLE D
[2]  
BRYANT RE, 1980, LAMBDA, V1, P46
[3]   MOTIS - MOS TIMING SIMULATOR [J].
CHAWLA, BR ;
GUMMEL, HK ;
KOZAK, P .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1975, 22 (12) :901-910
[4]  
Courtois B., 1981, VLSI 81. Very Large Scale Integration. Proceedings of the First International Conference on Very Large Scale Integration, P341
[5]  
GALIAY J, 1980, IEEE T COMPUT, V29, P527, DOI 10.1109/TC.1980.1675614
[6]   A UNIFIED SWITCHING THEORY WITH APPLICATIONS TO VLSI DESIGN [J].
HAYES, JP .
PROCEEDINGS OF THE IEEE, 1982, 70 (10) :1140-1151
[7]  
HAYES JP, 1981, 2ND CALTECH C VLSI P, P455
[8]  
JOHNSON W, 1980, J DIGITAL SYST, V4, P305
[9]  
KAWAI M, 1984, UNPUB 21ST P DES AUT
[10]  
Mead C., 1980, INTRO VLSI SYSTEMS
12