An Area-Efficient Euclid Architecture with Low Latency

This paper describes a new area-efficient Euclid Architecture with low latency based on the improvement of Euclid algorithm in Reed-Solomon (RS) decoding. The Euclid algorithm is improved by simplifying the process of data swap, which is needed in the original algorithm. Based on the improved algorithm, an area-efficient Euclid architecture with low latency is proposed, which can save time and area compared to the previous architectures based on the original Euclid algorithm. The proposed architecture uses only 4 finite field multipliers and 2 modulo-2 adders. Register addressing instead of register shifting is used in this architecture, which can save time. This architecture is simple and suitable for Very Large Scale Integration (VLSI) implementation.