DESIGN TECHNIQUES FOR HIGH-SPEED, HIGH-RESOLUTION COMPARATORS

This paper describes precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages. Following a review of conventional offset cancellation techniques, circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented. The BiCMOS comparator consists of a preamplifier followed by two regenerative stages and achieves an offset of 200 muV at a 10-MHz clock rate while dissipating 1.7 mW. In the CMOS comparator offset cancellation is used in both a single-stage preamplifier and a subsequent latch to achieve an offset of less than 300 muV at comparison rates as high as 10 MHz, with a power dissipation of 1.8 mW.