A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp

被引：5
|
作者：
Pan Hongwei [1 ]
Liu Siyang [1 ]
Sun Weifeng [1 ]
机构：
[1] Southeast Univ, Natl ASIC Syst Engn Res Ctr, Nanjing 210096, Jiangsu, Peoples R China
来源：
JOURNAL OF SEMICONDUCTORS | 2013年 / 34卷 / 01期
关键词：
ESD protection; ESD robustness; SCR-LDMOS; latch-up; holding voltage;
D O I：
10.1088/1674-4926/34/1/014007
中图分类号：
O469 [凝聚态物理学];
学科分类号：
070205 ;
摘要：
The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure, when used in power-rail ESD (electro-static discharge) clamp circuits. In order to eliminate latch-up risk, this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current. The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.
引用
收藏
页数：5
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