A HIGH-SPEED SENSING SCHEME FOR 1T DYNAMIC RAMS UTILIZING THE CLAMPED BIT-LINE SENSE AMPLIFIER

被引：14

作者：

BLALOCK, TN ^{[1
]}

JAEGER, RC ^{[1
]}

机构：

[1] AUBURN UNIV,DEPT ELECT ENGN,ALABAMA MICROELECTR SCI & TECHNOL TR,AUBURN,AL 36849

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1992年 / 27卷 / 04期

关键词：

D O I：

10.1109/4.126552

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to initial bit-line difference voltage. The CBLSA maintains a low-impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power.

引用

页码：618 / 625

页数：8

共 41 条

[31] A 0.7 V Single-Supply SRAM With 0.495 μm2 Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme [J].

Kushida, Keiichi ;

Suzuki, Azuma ;

Fukano, Gou ;

Kawasumi, Atsushi ;

Hirabayashi, Osamu ;

Takeyama, Yasuhisa ;

Sasaki, Takahiko ;

Katayama, Akira ;

Fujimura, Yuki ;

Yabe, Tomoaki .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (04) :1192-1198

[32] A 500-MHz High-Speed, Low-Power Ternary CAM Design Using Selective Match Line Sense Amplifier in 65nm CMOS [J].

Nagakarthik, T. ;

Choi, Jun Rim .

2015 6th International Conference on Information and Communication Systems (ICICS), 2015, :60-63

[33] A 0.5-μm, 3-V, 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor [J].

Ogiwara, R ;

Tanaka, S ;

Itoh, Y ;

Miyakawa, T ;

Takeuchi, Y ;

Doumae, SM ;

Takenaka, H ;

Kunishima, I ;

Shuto, S ;

Hidaka, O ;

Ohtsuki, S ;

Tanaka, S .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (04) :545-551

[34] Dual-Input Stacked Inverter-Based Single-Ended DRAM Sense Amplifier Using BL Switches for Low-Power High-Speed Sensing [J].

Lim, Sehee ;

Jung, In Jun ;

Kim, Gi Seok ;

Ko, Dong Han ;

Lee, Sumin ;

Jung, Seong-Ook .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2025, 60 (06) :2096-2105

[35] A 0.9V 1T1C SBT-based embedded non-volatile FeRAM with a reference voltage scheme and multi-layer shielded bit-line structure [J].

Yamaoka, K ;

Iwanari, S ;

Murakuki, Y ;

Hirano, H ;

Sakagami, M ;

Nakakuma, T ;

Miki, T ;

Gohou, Y .

2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 :50-51

[36] A 0.7V single-supply SRAM with 0.495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme [J].

Kushida, Keiichi ;

Suzuki, Azuma ;

Fukano, Gou ;

Kawasumi, Atsushi ;

Hirabayashi, Osamu ;

Takeyama, Yasuhisa ;

Sasaki, Takahiko ;

Katayama, Akira ;

Fujimura, Yuuki ;

Yabe, Tomoaki .

2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2008, :46-47

[37] Area-Improved High-Speed Hybrid 1-bit Full Adder Circuit Using 3T-XNOR Gate [J].

Kadu, Chaitali P. ;

Sharma, Manish .

2017 INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION, CONTROL AND AUTOMATION (ICCUBEA), 2017,

[38] A 0.7V single-supply SRAM with 0-495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme [J].

Kushida, Keiichi ;

Suzuki, Azuma ;

Fukano, Gou ;

Kawasumi, Atsushi ;

Hirabayashi, Osamu ;

Takeyama, Yasuhisa ;

Sasaki, Takahiko ;

Katayama, Akira ;

Fujimura, Yuuki ;

Yabe, Tomoaki .

2008 IEEE SYMPOSIUM ON VLSI CIRCUITS, 2008, :37-38

[39] Design Analysis and Dynamic Modeling of a High-Speed 3T1R Pick-and-Place Parallel Robot [J].

Wu, Guanglei ;

Bai, Shaoping ;

Hjornet, Preben .

RECENT ADVANCES IN MECHANISM DESIGN FOR ROBOTICS, 2015, 33 :285-295

[40] 5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology [J].

Kulkarni, Jaydeep P. ;

Keane, John ;

Koo, Kyung-Hoae ;

Nalam, Satyanand ;

Guo, Zheng ;

Karl, Eric ;

Zhang, Kevin .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017, 52 (01) :229-239

← 1 2 3 4 5 →