MULTIPROCESSOR DSP WITH MULTISTAGE SWITCHING NETWORK FOR VIDEO CODING

被引:1
|
作者
OKUMURA, Y
IRIE, K
KISHIMOTO, R
机构
[1] NTT Transmission Systems Laboratories, Yokosuka-shi
关键词
D O I
10.1109/26.87183
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper proposes a dynamic load balancing method using a multistage switching network to solve one of the greatest problems in multiprocessor DSP's for video coding: load concentration on certain processors. This method balances the processing load by distributing the total load among the processor elements having smaller loads. The load distribution is performed by the multistage switching network, which transmits the load quantity information within the network. A scheduling method for a motion picture coding algorithm using multiprocessor DSP's is also proposed. This scheduling method takes full advantage of the multistage switching network functions when distributing the processing load and sorting the processed results. By using computer simulation, multiprocessor DSP performance with the proposed method is shown to be double that of a conventional multiprocessor DSP when an initially unbalanced load is allocated to the processors, as in picture coding for TV conferences.
引用
收藏
页码:938 / 946
页数:9
相关论文
共 50 条
  • [1] MULTIPROCESSOR DSP WITH MULTISTAGE SWITCHING NETWORK AND ITS SCHEDULING FOR IMAGE-PROCESSING
    OKUMURA, Y
    IRIE, K
    KISHIMOTO, R
    VISUAL COMMUNICATIONS AND IMAGE PROCESSING IV, PTS 1-3, 1989, 1199 : 1106 - 1115
  • [2] Load balancing method for multiprocessor image DSPs using a multistage switching network
    Okumura, Yasuyuki
    Irie, Kazunari
    Kishimoto, Ryozo
    Journal of information processing, 1992, 15 (02) : 301 - 308
  • [3] Mapping of video decoder software on a VLIW DSP multiprocessor
    Freimann, A
    Brune, T
    Pirsch, P
    MULTIMEDIA HARDWARE ARCHITECTURES 1998, 1998, 3311 : 67 - 78
  • [4] Multistage motion vector quantization for video coding
    Hwang, WJ
    Huang, YC
    OPTICAL ENGINEERING, 2000, 39 (07) : 1994 - 2002
  • [5] The performance of the cedar multistage switching network
    Torrellas, J
    Zhang, Z
    IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 1997, 8 (04) : 321 - 336
  • [6] Performance of the Cedar multistage switching network
    Univ of Illinois at Urbana-Champaign, Urbana, United States
    IEEE Trans Parallel Distrib Syst, 4 (321-336):
  • [7] Architecture for video coding on a processor with an ARM and DSP cores
    Yung-Sung Huang
    Bin-Chang Chieu
    Multimedia Tools and Applications, 2011, 54 : 527 - 543
  • [8] Architecture for video coding on a processor with an ARM and DSP cores
    Huang, Yung-Sung
    Chieu, Bin-Chang
    MULTIMEDIA TOOLS AND APPLICATIONS, 2011, 54 (02) : 527 - 543
  • [9] Evaluation of a multistage switching network with broadcast traffic
    MirFakhraei, N
    ELECTRONICS INDUSTRIES FORUM OF NEW ENGLAND - PROFESSIONAL PROGRAM PROCEEDINGS, 1997, : 143 - 147
  • [10] Video Streaming with Network Coding
    Nguyen, Kien
    Nguyen, Thinh
    Cheung, Sen-Ching
    JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2010, 59 (03): : 319 - 333