GATE-DELAY-FAULT TESTABILITY PROPERTIES OF MULTIPLEXOR-BASED NETWORKS

被引：1

作者：

ASHAR, P

DEVADAS, S

KEUTZER, K

机构：

[1] NEC USA,C&C RES LABS,PRINCETON,NJ 08540

[2] MIT,DEPT ELECT ENGN & COMP SCI,CAMBRIDGE,MA 02139

[3] SYNOPSYS INC,MT VIEW,CA 94043

来源：

FORMAL METHODS IN SYSTEM DESIGN | 1993年 / 2卷 / 01期

关键词：

SYNTHESIS FOR TEST; STUCK-AT FAULTS; GATE-DELAY FAULTS; BINARY DECISION DIAGRAMS (BDDS);

D O I：

10.1007/BF01383945

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

We investigate the gate-delay-fault testability properties of multilevel, multiplexor-based logic circuits. Based on this investigation, we describe a procedure for synthesizing gate-delay-fault testable multilevel circuits. The procedure involves the construction of a multilevel circuit from a general, unordered Binary Decision Diagram (BDD) by replacing vertices of the BDD with multiplexors. The procedure relies on the following result derived in this article: If the multilevel circuit constructed from the BDD is initially fully single stuck-at fault testable, or made fully single stuck-at fault testable by redundancy removal, then it is completely robustly gate-delay-fault testable. Once the initial gate-delay-fault testable circuit has been obtained, constrained algebraic factorization is used to improve the area and performance characteristics without compromising testability. Unlike previous techniques for synthesizing robustly gate-delay-fault testable circuits, this procedure can be used to synthesize fully testable circuits directly from nonflattenable, logic-level implementations.

引用

页码：93 / 112

页数：20

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