BURIED P-LAYER SAINT FOR VERY HIGH-SPEED GAAS LSIS WITH SUBMICROMETER GATE LENGTH

被引：60

作者：

YAMASAKI, K

KATO, N

HIRAYAMA, M

机构：

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1985年 / 32卷 / 11期

关键词：

D O I：

10.1109/T-ED.1985.22289

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：2420 / 2425

页数：6

共 13 条

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KATO, N ;

MATSUOKA, Y ;

OHWADA, K ;

MORIYA, S .

IEEE ELECTRON DEVICE LETTERS, 1983, 4 (11) :417-419

[2]

MATSUMOTO K, 1984, 42ND ANN DEV RES C S

[3]

MIYANAGA H, 1984, 16TH C SOL STAT DEV, P225

[4]

NAKAMURA H, 1984, 16TH P C SOL STAT DE, P395

[5]

OHMORI M, 1984, 11TH INT S GALL ARS

[6]

OHNISHI T, 1984, 16TH P C SOL STAT DE, P391

[7]

SADLER RA, 1983, APPL PHYS LETT, V43, P856

[8]

UMEMOTO Y, 1982, 1982 GAAS IC S NEW O, P173

[9]

Yamasaki K., 1982, International Electron Devices Meeting. Technical Digest, P166

[10] SELF-ALIGN IMPLANTATION FOR N+-LAYER TECHNOLOGY (SAINT) FOR HIGH-SPEED GAAS ICS [J].

YAMASAKI, K ;

ASAI, K ;

MIZUTANI, T ;

KURUMADA, K .

ELECTRONICS LETTERS, 1982, 18 (03) :119-121

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