Comparison of Preemption Schemes for Partially Reconfigurable FPGAs

被引：13

作者：

Jozwik, Krzysztof ^{[1
]}

Tomiyama, Hiroyuki ^{[2
]}

Edahiro, Masato ^{[1
]}

Honda, Shinya ^{[1
]}

Takada, Hiroaki ^{[1
]}

机构：

[1] Nagoya Univ, Grad Sch Informat Sci, Nagoya, Aichi 4348603, Japan

[2] Ritsumeikan Univ, Coll Sci & Engn, Shiga 5258577, Japan

来源：

IEEE EMBEDDED SYSTEMS LETTERS | 2012年 / 4卷 / 02期

关键词：

Dynamic reconfiguration; FPGA; runtime reconfiguration;

D O I：

10.1109/LES.2012.2193660

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Preemption techniques for hardware (HW) tasks have been studied in order to improve system responsiveness at the task level and improve utilization of the FPGA area. This letter presents a fair comparison of existing state-of-the-art pre-emption approaches from the point of view of their capabilities and limitations as well as impact on static and dynamic properties of the task. In comparison, we use a set of cryptographic, image, and audio processing HW tasks and perform tests on a common platform based on a Virtex-4 FPGA from Xilinx. Furthermore, we propose the preemption as a method which can effectively increase FPGA utilization in case of HW tasks used as CPU accelerators in systems with memory protection and virtualization.

引用

页码：45 / 48

页数：4