A new DSP DPLL demodulator with a difference

被引：1
作者：
Biswas, BN
Biswas, S
Mondal, D
Lahiri, P
Mukhopadhyay, D
Sinha, AP
机构：
[1] Radionics Laboratory, Physics Department, Burdwan University, Burdwan
来源：
IETE TECHNICAL REVIEW | 1995年 / 12卷 / 03期
关键词：
D O I：
10.1080/02564602.1995.11416531
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The major limitations of the existing varieties of DSP DPLL are that (i) the highest loop gain is 2.0, and (ii) the loop noise phase error increases with the loop gain, which seriously affect their performance as a demodulator. The proposed DSP DPLL structure not only does cross the limiting gain of 2.0 but also reduces the noise phase error variance to a large extent without sacrificing the loop gain. These are demonstrated through analysis and computer imulation results.
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页码：227 / 235
页数：9
相关论文
共 10 条
[1]   NEW SOFTWARE-CONTROLLED DIGITAL PHASE-LOCKED LOOP [J].
BISWAS, BN ;
BHATTACHARYA, AK ;
PAL, P ;
MONDAL, D ;
RAY, SK ;
DE, R .
ELECTRONICS LETTERS, 1989, 25 (16) :1097-1098
[2]  
Biswas BN., 1988, PHASE LOCK THEORIES
[3]   FIRST-ORDER DISCRETE PHASE-LOCKED LOOP WITH APPLICATIONS TO DEMODULATION OF ANGLE-MODULATED CARRIER [J].
GILL, GS ;
GUPTA, SC .
IEEE TRANSACTIONS ON COMMUNICATIONS, 1972, CO20 (03) :454-&
[4]  
Hagiwara M., 1985, Transactions of the Institute of Electronics and Communication Engineers of Japan, Part B, VJ68B, P646
[5]  
Hata M., 1986, Journal of the Institute of Electronics and Communication Engineers of Japan, V69, P922
[6]  
IWANAMI Y, P GLOBECOM 87, P1319
[7]  
KLAPPER J, 1972, PHASELOCKED FREQUENC
[8]  
PASTERNACK G, 1968, BELL SYST TECH J, V47, P2207
[9]   GRAPHICAL ANALYSIS OF A DIGITAL PHASE-LOCKED LOOP [J].
RUSSO, F .
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS, 1979, 15 (01) :88-94
[10]   DISCRETE-TIME ANALYSES OF NONUNIFORM SAMPLING FIRST-ORDER AND SECOND-ORDER DIGITAL PHASE LOCK LOOPS [J].
WEINBERG, A ;
LIU, B .
IEEE TRANSACTIONS ON COMMUNICATIONS, 1974, CO22 (02) :123-137
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