IMPACT OF SCALING DOWN ON LOW-FREQUENCY NOISE IN SILICON MOS-TRANSISTORS

A theoretical analysis of the impact of scaling down on the low frequency noise characteristics of silicon MOS transistors is presented. This analysis is based on the assumption that low frequency noise in large area MOS devices arises from the superposition of many RTS (random telegraph signal) fluctuators. An analytical formula for the input gate voltage noise in large area devices is derived from the RTS approach, reconciling the McWhorter and the RTS approaches. Moreover, we show that. for a realistic scaling law, the miniaturization of the devices will lead to an increase of the mean noise level linearly with the scaling factor and to a substantial (almost-equal-to three orders wide) sample-to-sample noise level dispersion. whereas for a classical scaling law, the mean noise is found to be independent of scaling. Finally, it is shown that the miniaturization will also result in a strong evolution of the noise spectra from 1/f to Lorentzian like for devices with channel lengths from 1 to 0.1-mu-m.