TERNARY DYNAMIC DIFFERENTIAL NO-RACE LOGIC

被引:3
作者
HERRFELD, A
HENTSCHKE, S
机构
[1] 1PM-Digitaltechnik, Kassel, 34121, U-Ghk Kassel-FB 16
关键词
D O I
10.1080/00207219508926251
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A digital dynamic switching technique for CMOS that can realize ternary functions is introduced. Besides the ease of the design of the switching functions, the positive properties of a low capacitive load, a high noise margin and the need for a standard CMOS process technology should be emphasized. Furthermore, no buffering between cascaded gates is necessary. The effectiveness of the ternary switching technology in contrast to a binary one is demonstrated by the example of an array multiplier.
引用
收藏
页码:63 / 79
页数:17
相关论文
共 28 条
[1]  
BARAK AB, 1977, IEEE T COMPUT, V26, P823, DOI 10.1109/TC.1977.1674922
[2]  
BRITRAN M, 1971, AEU-ARCH ELEKTRON UB, V25, P387
[3]   A COMPARISON OF CMOS CIRCUIT TECHNIQUES - DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC VERSUS CONVENTIONAL LOGIC [J].
CHU, KM ;
PULFREY, DL .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (04) :528-532
[4]   DESIGN PROCEDURES FOR DIFFERENTIAL CASCODE VOLTAGE SWITCH CIRCUITS [J].
CHU, KM ;
PULFREY, DI .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (06) :1082-1087
[5]   NORA - A RACEFREE DYNAMIC CMOS TECHNIQUE FOR PIPELINED LOGIC STRUCTURES [J].
GONCALVES, NF ;
DEMAN, HJ .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (03) :261-266
[7]  
Heller L.G., 1984, ISSCC, P16
[8]   CMOS TERNARY DYNAMIC DIFFERENTIAL LOGIC [J].
HERRFELD, A ;
HENTSCHKE, S .
ELECTRONICS LETTERS, 1994, 30 (10) :762-763
[9]   CMOS TERNARY DYNAMIC NORA LOGIC [J].
HERRFELD, A ;
HENTSCHKE, S .
ELECTRONICS LETTERS, 1994, 30 (17) :1370-1371
[10]  
HERRFELD A, 1994, ELECTRON LETT, V30, P1897