A 60-NS 16-MBIT CMOS DRAM WITH A TRANSPOSED DATA-LINE STRUCTURE

被引：23

作者：

AOKI, M

NAKAGOME, Y

HORIGUCHI, M

TANAKA, H

IKENAGA, S

ETOH, J

KAWAMOTO, Y

KIMURA, S

TAKEDA, E

SUNAMI, H

ITOH, K

机构：

[1] HITACHI LTD,RECH FONDAMENTALE RES LAB,KOKUBUNJI,TOKYO 185,JAPAN

[2] HITACHI VLSI ENGN CORP,KODAIRA,TOKYO 187,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1988年 / 23卷 / 05期

关键词：

D O I：

10.1109/4.5932

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1113 / 1119

页数：7

共 12 条

[1]

AOKI M, 1988, FEB ISSCC DIG TECH P, P250

[2]

GRAY PR, 1983, ANAL DESIGN ANALOG I, pCH8

[3] DUAL-OPERATING-VOLTAGE SCHEME FOR A SINGLE 5-V 16-MBIT DRAM [J].

HORIGUCHI, M ;

AOKI, M ;

TANAKA, H ;

ETOH, J ;

NAKAGOME, Y ;

IKENAGA, S ;

KAWAMOTO, Y ;

ITOH, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (05) :1128-1132

[4]

IKENAGA S, 1987, OCT C IECE JAP C REC, P1

[5]

INOUE M, 1988, FEB ISSCC, P246

[6] HALF-V CC SHEATH-PLATE CAPACITOR DRAM CELL WITH SELF-ALIGNED BURIED PLATE WIRING [J].

KAGA, T ;

KAWAMOTO, Y ;

KURE, T ;

NAKAGOME, Y ;

AOKI, M ;

SUNAMI, H ;

MAKINO, T ;

OHKI, N ;

ITOH, K .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1988, 35 (08) :1257-1263

[7] AN OPTICALLY DELINEATED 4.2-MU-M2 SELF-ALIGNED ISOLATED-PLATE STACKED-CAPACITOR DRAM CELL [J].

KIMURA, SI ;

KAWAMOTO, Y ;

HASEGAWA, N ;

HIRAIWA, A ;

NAKAGOME, Y ;

AOKI, M ;

KISU, T ;

SUNAMI, H ;

ITOH, K .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1988, 35 (10) :1591-1595

[8]

MANO T, 1987, FEB ISSCC, P22

[9] THE IMPACT OF DATA-LINE INTERFERENCE NOISE ON DRAM SCALING [J].

NAKAGOME, Y ;

AOKI, M ;

IKENAGA, S ;

HORIGUCHI, M ;

KIMURA, S ;

KAWAMOTO, Y ;

ITOH, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (05) :1120-1127

[10]

WATANABE S, 1988, FEB ISSCC, P248

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