BALANCED PHASE-LOCKED LOOPS FOR OPTICAL HOMODYNE RECEIVERS - PERFORMANCE ANALYSIS, DESIGN CONSIDERATIONS, AND LASER LINEWIDTH REQUIREMENTS

被引:144
作者
KAZOVSKY, LG
机构
关键词
D O I
10.1109/JLT.1986.1074698
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:182 / 195
页数:14
相关论文
共 50 条
[31]   Design of a high performance charge pump circuit for low voltage phase-locked loops [J].
Sun, Yuan ;
Sick, Liter ;
Song, Pengyu .
2007 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, VOLS 1 AND 2, 2007, :271-274
[32]   Design of the clock recovery circuit with a phase-locked loop for 40 Gb/s optical receivers [J].
Park, CH ;
Woo, DS ;
Kim, KW ;
Lim, SK .
34TH EUROPEAN MICROWAVE CONFERENCE, VOLS 1-3, CONFERENCE PROCEEDINGS, 2004, :757-759
[33]   Dynamic phasor analysis and design of phase-locked loops for single phase grid connected converters [J].
Rashed, Mohamed ;
Klumpner, Christian ;
Asher, Greg .
COMPEL-THE INTERNATIONAL JOURNAL FOR COMPUTATION AND MATHEMATICS IN ELECTRICAL AND ELECTRONIC ENGINEERING, 2015, 34 (04) :1122-1143
[34]   Design and noise analysis of a fully-differential charge pump for phase-locked loops [J].
宫志超 ;
卢磊 ;
廖友春 ;
唐长文 .
半导体学报, 2009, 30 (10) :126-131
[35]   Design and noise analysis of a fully-differential charge pump for phase-locked loops [J].
Gong Zhichao ;
Lu Lei ;
Liao Youchun ;
Tang Zhangwen .
JOURNAL OF SEMICONDUCTORS, 2009, 30 (10)
[36]   Design and Analysis of DTC-Free ΔΣ Bang-Bang Phase-Locked Loops [J].
Wan, Zixiang ;
Rhee, Woogeun ;
Wang, Zhihua .
2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2021,
[37]   Design of a Low-spur Charge Pump for High Performance CMOS Phase-locked Loops [J].
Shi, Zhan ;
Yu, Jun ;
Tang, Zhen'an ;
Cai, Hong ;
Feng, Chong .
Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology, 2017, 39 (06) :1472-1478
[38]   Ring-VCO-based phase-locked loops for clock generation - design considerations and state-of-the-art [J].
Yang, Shiheng ;
Yin, Jun ;
Liu, Yueduo ;
Zhu, Zihao ;
Bao, Rongxin ;
Lin, Jiahui ;
Li, Haoran ;
Li, Qiang ;
Mak, Pui-In ;
Martins, Rui P. .
CHIP, 2023, 2 (02)
[39]   The Z-domain method for analysis and design of high order digital phase-locked loops [J].
Azzam, BF .
MICROWAVE JOURNAL, 2000, 43 (03) :110-+
[40]   Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops [J].
Marucci, Giovanni ;
Levantino, Salvatore ;
Maffezzoni, Paolo ;
Samori, Carlo .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61 (01) :26-36