A 512 16-B BIT-SERIAL SORTER CHIP

被引：10

作者：

AFGHAHI, M

机构：

[1] Lsi Design Center, University of Linköping, 581 83, Linköping

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1991年 / 26卷 / 10期

关键词：

D O I：

10.1109/4.90101

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A hardware algorithm is presented for sorting. This algorithm is based on a highly piplined bit-serial architecture. The processing time of this sorter is linearly proportional to the number of data. Sorting cells are much smaller and simpler than previously reported sorter cells. A single chip sorting 512 16-b keys is designed with a 2-mu-m process and simulated at 240 MHz. The area.time performance of this chip is more than 60 times more efficient than previously reported sorting engines.

引用

页码：1452 / 1457

页数：6

共 13 条

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