WIDE-BAND PHASE-LOCKED LOOP SYNTHESIZER USING LINEAR FREQUENCY VARIATION DIRECT DIGITAL SYNTHESIZER AS REFERENCE OSCILLATOR

被引:0
作者
ITOH, K
IIDA, A
KANAGAWA, Y
机构
[1] MITSUBISHI ELECTR CORP,MICROWAVE SYST LABS,KAMAKURA,KANAGAWA 247,JAPAN
[2] MITSUBISHI ELECTR CORP,COMMUN EQUIPMENT WORKS,AMAGASAKI,HYOGO 661,JAPAN
来源
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART I-COMMUNICATIONS | 1995年 / 78卷 / 09期
关键词
SPREAD SPECTRUM; SYNTHESIZER; DDS; PLL; LOCK-IN RANGE; MICROWAVE;
D O I
10.1002/ecja.4410780908
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A wideband phase-locked loop (PLL) synthesizer is proposed in which a linear frequency variation direct digital synthesizer (LFDDS) is used as a reference oscillator and a frequency variation band can be widened up to the full tunable range of voltage controlled oscillator (VCO) by frequency hopping within the lock-in range of PLL. A theoretical study is made and experimental results ale explained. At first, assuming continuous frequency variation of LFDDS, transient behavior of frequency difference between two input signals of phase comparator of PLL is determined. Next, the condition for frequency variation speed of LFDDS is derived so that phase locking can be obtained using the maximum value of this frequency difference. Then the quantized frequency variation of LFDDS is assumed, transient behavior of the frequency difference is determined, and its difference from the continuous variation is clarified. A 6-GHz band PLL synthesizer is fabricated, and the theory's validity is confirmed through experiments. Using LFDDS, a frequency setting time for a PLL synthesizer increases less than 10 percent for five times wider operation bandwidth. Performing experiments in 6-GHz band, we obtained an operation bandwidth of 23 percent and so frequency hopping can be performed. Moreover, a frequency setting time of 50 mu s and spurious level of -55 dBc were obtained.
引用
收藏
页码:79 / 90
页数:12
相关论文
共 50 条
[31]   Optimized Charge Pump and Nonlinear Phase Frequency Detector for a Ka-Band Phase-Locked Loop in 90-nm CMOS Process [J].
Tang, Lu ;
Wang, Zhigong ;
Fan, Tiantian ;
Liu, Faen ;
Zhang, Changchun .
IEICE TRANSACTIONS ON ELECTRONICS, 2019, E102C (11) :825-832
[32]   A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop [J].
Shu, Guanghua ;
Saxena, Saurabh ;
Choi, Woo-Seok ;
Talegaonkar, Mrunmay ;
Inti, Rajesh ;
Elshazly, Amr ;
Young, Brian ;
Hanumolu, Pavan Kumar .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2014, 49 (04) :1036-1047
[33]   Multiple frequency digital phase-locked loop based on multi-phase clock divider with constant pulse interval [J].
Yahara M. ;
Fujimoto K. ;
Kiyota H. .
IEEJ Transactions on Electronics, Information and Systems, 2018, 138 (04) :387-394
[34]   A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC [J].
Nandwana, Romesh Kumar ;
Saxena, Saurabh ;
Elshazly, Amr ;
Mayaram, Kartikeya ;
Hanumolu, Pavan Kumar .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64 (02) :283-295
[35]   Multiple-frequency digital phase-locked loop based on multiphase clock divider with constant pulse interval [J].
Yahara, Mitsutoshi ;
Fujimoto, Kuniaki ;
Kiyota, Hideo .
ELECTRONICS AND COMMUNICATIONS IN JAPAN, 2018, 101 (07) :40-47
[36]   Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting [J].
Yu, G. ;
Wang, Y. ;
Yang, H. ;
Wang, H. .
IET CIRCUITS DEVICES & SYSTEMS, 2010, 4 (03) :207-217
[37]   A current-configurable charge pump with current mismatch compensation for wide output frequency range phase-locked loop [J].
Han, Jiahui ;
Tong, Xingyuan .
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2024, 177
[38]   20 GHz Clock Frequency ROM-Less Direct Digital Synthesizer Comprising Unique Phase Control Unit in 0.25 μm SiGe Technology [J].
Shrestha, Amit ;
Moll, Jochen ;
Raemer, Adam ;
Hrobak, Michael ;
Krozer, Viktor .
2018 13TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC), 2018, :206-209
[39]   An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking [J].
Rehman, Muhammad Riaz Ur ;
Hejazi, Arash ;
Ali, Imran ;
Asif, Muhammad ;
Oh, Seongjin ;
Kumar, Pervesh ;
Pu, Younggun ;
Yoo, Sang-Sun ;
Hwang, Keum Cheol ;
Yang, Youngoo ;
Jung, Yeonjae ;
Huh, Hyungki ;
Kim, Seokkee ;
Yoo, Joon-Mo ;
Lee, Kang-Yoon .
IEEE ACCESS, 2021, 9 :152984-152992
[40]   Fractional spur reduction technique using 45° phase dithering in phase interpolator based all-digital phase-locked loop [J].
Ko, J. ;
Heo, M. ;
Lee, J. ;
Kim, C. ;
Lee, M. .
ELECTRONICS LETTERS, 2016, 52 (23) :1920-1922