SUB-1-V SWING INTERNAL BUS ARCHITECTURE FOR FUTURE LOW-POWER ULSIS

A new bus architecture is proposed for reducing the operating power of future ULSI's. This architecture will relieve the constraint of the conventional supply voltage scaling, which makes it difficult to achieve both high speed and a low standby current if the supply voltage is scaled to less than 2 V. It employs new types of bus driver circuits and bus receiver circuits to reduce the bus signal swing while maintaining a low standby current. The bus driver circuit has a source offset configuration through the use of low-V(T) MOSFET's and an internal supply voltage corresponding to the reduced signal swing. Bus delay is almost halved with this driver when operated at 0.6-V swing and 2-V supply. The bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of new bus driver and bus receiver enables the bus swing to be reduced to one-third that of the conventional architecture while maintaining a high-speed data transmission and a low standby current. A test circuit is designed and fabricated using 0.3-mum processes. The operation of the proposed architecture was verified, and further improvements in the speed performance are expected by device optimization. The proposed architecture is promising for reducing the operating power of future ULSI's.