High-Speed Low-Power MCML Nanometer Circuits with Near-Threshold Computing

被引：5

作者：

Hu, Jianping ^{[1
]}

Ni, Haiyan ^{[1
]}

Xia, Yinshui ^{[1
]}

机构：

[1] Ningbo Univ, Fac Informat Sci & Technol, Ningbo, Zhejiang, Peoples R China

来源：

JOURNAL OF COMPUTERS | 2013年 / 8卷 / 01期

基金：

中国国家自然科学基金;

关键词：

nanometer circuit; near-threshold computing; MOS current-mode logic; low power; high-speed operating;

D O I：

10.4304/jcp.8.1.129-135

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

In this paper, the standard cells of the high-speed low-power MCML circuits with near-threshold computing are developed. The basic MCML standard cells include buffer/inverter, AND/NAND, XOR/XNOR, multiplexer, and full adder. The layout, abstract design and standard-cell characters of near-threshold MCML basic cells are described at a NCSU FreePDK 45nm technology. The 2-bit multiplier is verified by using the MCML cells. For normal supply voltage, the MCML basic gates can save more energy and have better performance than the traditional CMOS counterparts at 1GHz or higher operation frequencies. Near-threshold computing for MCML circuits is investigated by scaling down the supply voltage. The results show that the power consumption of MCML circuits that operate on near-threshold regions can be reduced without performance degrading.

引用

页码：129 / 135

页数：7

共 13 条

[1]

Abdulkarim OM, 2007, GLSVLSI'07: PROCEEDINGS OF THE 2007 ACM GREAT LAKES SYMPOSIUM ON VLSI, P212

[2] Design strategies for source coupled logic gates [J].

Alioto, M ;

Palumbo, G .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2003, 50 (05) :640-654

[3] Power reduction via an MTCMOS implementation of MOS current mode logic [J].

Anis, MH ;

Elmasry, MI .

15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2002, :193-197

[4] A design methodology for low-power MCML ring oscillators [J].

Caruso, Giuseppe ;

Macchiarella, Alessio .

2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3, 2007, :675-678

[5] MOS current mode circuits: Analysis, design, and variability [J].

Hassan, H ;

Anis, M ;

Elmasry, M .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2005, 13 (08) :885-898

[6] Low-power multi-threshold MCML: Analysis, design, and variability [J].

Hassan, Hassan ;

Anis, Mohab ;

Elmasry, Mohamed .

MICROELECTRONICS JOURNAL, 2006, 37 (10) :1097-1104

[7] Design and analysis of low-voltage current-mode logic buffers [J].

Heydari, P .

4TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2003, :293-298

[8] An Efficient Delay Model for MOS Current-Mode Logic Automated Design and Optimization [J].

Musa, Osman ;

Shams, Maitham .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (08) :2041-2052

[9] MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments [J].

Musicer, JM ;

Rabaey, J .

ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2000, :102-107

[10] Differential current switch logic: A low power DCVS logic family [J].

Somasekhar, D ;

Roy, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (07) :981-991

← 1 2 →