AN EFFICIENT TIMING MODEL FOR CMOS COMBINATIONAL LOGIC GATES

被引：16
作者：
WU, CY
HWANG, JS
CHANG, C
CHANG, CC
机构：
[1] ELECTR RES & SERV ORG,IND TECHNOL RES INST,HSINCHU,TAIWAN
[2] NATL CHIAO TUNG UNIV,INST ELECTR,HSINCHU,TAIWAN
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1985年 / 4卷 / 04期
关键词：
D O I：
10.1109/TCAD.1985.1270164
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
18
引用
收藏
页码：636 / 650
页数：15
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