YIELD AND PERFORMANCE ENHANCEMENT THROUGH REDUNDANCY IN VLSI AND WSI MULTIPROCESSOR SYSTEMS

被引：32
作者：
KOREN, I
PRADHAN, DK
机构：
[1] TECHNION ISRAEL INST TECHNOL,DEPT COMP SCI,IL-32000 HAIFA,ISRAEL
[2] TECHNION ISRAEL INST TECHNOL,VLSI SYST RES CTR,IL-32000 HAIFA,ISRAEL
[3] UNIV MASSACHUSETTS,DEPT ELECT & COMP ENGN,AMHERST,MA 01003
来源：
PROCEEDINGS OF THE IEEE | 1986年 / 74卷 / 05期
关键词：
COMPUTER SYSTEMS; DIGITAL; -; Multiprocessing; REDUNDANCY; RELIABILITY; Evaluation;
D O I：
10.1109/PROC.1986.13532
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Fault-tolerant architectures that use redundancy for yield and performance improvement are considered. The authors present a unified framework through which existing architectures of VLSI processor arrays incorporating fault tolerance can be analyzed and new ones suggested. Several problems related to testing and reconfiguration of these arrays are also described. Both the distributed and centralized modes of testing are discussed. The last part of the work presents analytical models for the evaluation of reliability and yield improvement through redundancy.
引用
收藏
页码：699 / 711
页数：13
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