共 50 条
[31]
Sample and Hold Circuit with Clock Boosting
[J].
ICSPC'21: 2021 3RD INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND COMMUNICATION (ICPSC),
2021,
:197-201
[32]
A signal dependent clock feedthrough cancellation technique for switched current circuits
[J].
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS,
1997, 80 (09)
:26-34
[34]
A Sample and Hold with Clock booster for improved linearity
[J].
2019 6TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN),
2019,
:1058-1062
[36]
Elimination of nonlinear clock feedthrough in component-simulation switched-current circuits
[J].
ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6,
1998,
:A378-A381
[38]
TRANSIENT-RESPONSE OF SAMPLE-AND-HOLD CIRCUITS
[J].
ELECTRONICS LETTERS,
1980, 16 (04)
:123-124