共 50 条
[22]
A CMOS miller hold capacitance sample-and-hold circuit to reduce charge sharing effect and clock feedthrough
[J].
15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS,
2002,
:92-96
[23]
A 3.3 V, 10 Bits, Clock-Feedthrough Compensated Switched-Current Second Order Sigma-Delta Modulator
[J].
Analog Integrated Circuits and Signal Processing,
2004, 39
:81-87
[24]
A Chargepump with enhanced Current Matching and reduced Clock-Feedthrough in Wireless Sensor Nodes
[J].
2010 ASIA-PACIFIC MICROWAVE CONFERENCE,
2010,
:2291-2294
[25]
Analysis of mirror mismatch and clock-feedthrough in Bruton transformation switched current wave filters
[J].
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS,
2003, 150 (01)
:6-15
[27]
Switched capacitor circuits with compensator for clock feedthrough effects
[J].
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS,
1996, 79 (01)
:51-63
[29]
The testing of the sample-and-hold amplifier's feedthrough
[J].
ICEMI'2001: FIFTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT AND INSTRUMENTS, VOL 1, CONFERENCE PROCEEDINGS,
2001,
:244-247