REDUCED IMPLEMENTATION OF D-TYPE DET FLIP-FLOPS

One of the main disadvantages of using D-type double-edge triggered flip-flops (DET-FF's) in VLSI systems design is the number of transistors required. In this paper two new DET-FF circuits (one static, the other dynamic) are proposed in which the number of transistors is reduced to a number similar to that for classic single-edge triggered flip-flops (SET-FF's). Both new circuits not only behave correctly when operated at high frequency but also offer a good level of immunity to metastability problems (static) and race problems (dynamic), as well as presenting a simple straightforward layout. These considerations offer wider practical and economic applications for the use of DET-FF's in VLSI systems design.