CONSIDERATION OF BIT-DENSITY LIMITATIONS IN PLATED-WIRE MEMORY

被引：0

|

作者：

ORIHARA, S ^{[1
]}

KAWAKAMI, S ^{[1
]}

SAKAI, S ^{[1
]}

机构：

[1] FUJITSU LABS LTD,KAWASAKI,JAPAN

来源：

IEEE TRANSACTIONS ON MAGNETICS | 1973年 / MAG9卷 / 03期

关键词：

D O I：

10.1109/TMAG.1973.1067589

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

收藏

页码：507 / 511

页数：5

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