DESIGN OF SELF-CHECKING CIRCUITS FOR TEST DIAGNOSTICS OF DIGITAL DEVICES WITH MEMORY

被引:0
作者
SPERANSKY, DV
SHATOKHINA, NK
机构
来源
AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA | 1985年 / 03期
关键词
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
引用
收藏
页码:82 / 85
页数:4
相关论文
共 50 条
  • [41] DESIGN OF A SELF-CHECKING MICROPROGRAM CONTROL
    COOK, RW
    SISSON, WH
    STOREY, TF
    TOY, WN
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1973, C 22 (03) : 255 - 262
  • [42] Self-checking microprogrammed controller design
    Lala, PK
    Walker, A
    [J]. ICEMI'99: FOURTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOLS 1 AND 2, CONFERENCE PROCEEDINGS, 1999, : 555 - 559
  • [43] Self-checking synchronous controller design
    Kia, SM
    Parameswaran, S
    [J]. IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 1999, 146 (01): : 9 - 12
  • [44] ERROR-CORRECTING CODES AND SELF-CHECKING CIRCUITS
    PRADHAN, DK
    STIFFLER, JJ
    [J]. COMPUTER, 1980, 13 (03) : 27 - 37
  • [45] SYNTHESIS OF TOTALLY SELF-CHECKING SEQUENTIAL-CIRCUITS
    MAZNEV, VI
    [J]. AUTOMATION AND REMOTE CONTROL, 1977, 38 (06) : 913 - 920
  • [46] Automatic modification of sequential circuits for self-checking implementation
    Metra, C
    Di Francescantonio, S
    Omaña, M
    [J]. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2003, : 417 - 424
  • [47] On Evaluating the Signal Reliability of Self-checking Arithmetic Circuits
    Franco, Denis T.
    Vasconcelos, Mai C.
    Naviner, Lirida A. de B.
    Naviner, Jean-Francois
    [J]. SBCCI 2010: 23RD SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS, 2010, : 109 - 114
  • [48] A hyper optimal encoding scheme for self-checking circuits
    Lo, JC
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1996, 45 (09) : 1022 - 1030
  • [49] DESIGN OF SELF-CHECKING ITERATIVE NETWORKS
    DHAWAN, S
    DEVRIES, RC
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1988, 37 (09) : 1121 - 1125
  • [50] Self-checking design in Eastern Europe
    Piestrak, SJ
    [J]. IEEE DESIGN & TEST OF COMPUTERS, 1996, 13 (01): : 16 - 25