Low-power CMOS threshold-logic gate

被引：35
|
作者：
Avedillo, MJ
Quintana, JM
Rueda, A
Jimenez, E
机构：
[1] Departamento de Diseño Analógico, CNM, Universidad de Sevilla, 41012 Sevilla, Edif. C1CA, Avda. Reina Mercedes s/n
来源：
ELECTRONICS LETTERS | 1995年 / 31卷 / 25期
关键词：
logic circuits; integrated logic circuits; CMOS integrated circuits;
D O I：
10.1049/el:19951471
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new implementation of a threshold gate based on a latch-type comparator that does not consume static power is presented. Simulation results indicate high operation speed and low power consumption, which make it very attractive when used as a basic building block in digital design.
引用
收藏
页码：2157 / 2159
页数：3
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