A Pole-Zero Analysis Method Based on Signal-Flow Graphs for Analog IC

A method utilizing Mason's rule to derive the poles and zeros of the analog integrated circuits (IC) system separately based on the signal-flow graphs (SFG) is described in this paper. The numerator and denominator of transfer function can be derived separately through simple addition and subtraction to the forward-path gains and the loop gains of the SFG by this method. Besides, the poles and zeros can be obtained by some critical loop gains and forward-path gains. The number of the nontouching loops observed intuitively from the SFG determines the order of the transfer function as well as the number of the poles and zeros. Compared to the general Kirchhoff's voltage law (KVL) and Kirchhoff's current law (KCL), this method reduces the amount of manual calculation considerably. Also, the circuit parameters forming poles and zeros can be obtained based on its converted SFG. In addition, it is helpful to further understand the formation of poles and zeros. The nested-miller frequency compensation (NMC), a three-stage operational amplifier, as an example, is presented to illustrate the specific application of this method.