LOW-VOLTAGE BICMOS DYNAMIC LOGIC GATES

被引：1

作者：

CHEN, HP

WU, YP

机构：

[1] Dept. of Electrical Eng., National Taiwan University #1, Taipei 106-17, Rm. 319, Roosevelt Rd.

来源：

ELECTRONICS LETTERS | 1994年 / 30卷 / 22期

关键词：

BICMOS INTEGRATED CIRCUITS; LOGIC GATES;

D O I：

10.1049/el:19941263

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-supply-voltage BiCMOS logic gate is presented which can be used to form a pipelined system using the two-phase nonoverlapping clocks. The new BICMOS dynamic logic gates have no DC power dissipations and they have full voltage swings. It has been shown that the use of the described feedback technique provides a lower gale delay than previously reported low-voltage designs.

引用

页码：1849 / 1850

页数：2

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