ELECTRICAL ANALYSIS AND MODELING OF FLOATING-GATE FAULT

It is widely assumed that an open gate fault in a MOS transistor is equivalent to a stuck-at fault. In this paper we demonstrate that a floating gate transistor (FGT) is influenced by its topological environment. The equivalent gate-to-source voltage of the FGT depends on the initial charges trapped in the gate dioxide, the surrounding potential of metal lines and the drain-to-source voltage of the FGT itself. In the first part of this paper, an electrical study of the floating gate fault is presented. A theoretical model is proposed, taking into account the influence of the transistor's environment. Analytical expressions for the equivalent gate-to-source voltage are derived and the FGT's electrical operation mode is analyzed. In the second part, this model is validated by SPICE simulations and by actual device measurements. Finally, in the last part, the problem of testing for floating gate transistors is discussed.