IMPURITY DIFFUSION BEHAVIOR OF BIPOLAR-TRANSISTOR UNDER LOW-TEMPERATURE FURNACE ANNEALING AND HIGH-TEMPERATURE RTA AND ITS OPTIMIZATION FOR 0.5-MU-M BI-CMOS PROCESS

A low-temperature-processed (800-850-degrees-C) bipolar transistor design suitable for the high-performance 0.5-mu-m Bi-CMOS process is discussed. It has been found that insufficient activation of arsenic in the emitter, enhanced boron diffusion in the low-concentration base region, and insufficient arsenic diffusion from the poly Si are serious considerations, if low-temperature furnace annealing is used. If high-temperature RTA is used instead of low-temperature furnace annealing, these problems are resolved. Through impurity diffusion behavior and related electrical bipolar characteristics, the optimum conditions and structures for bipolar transistor design in the high-performance 0.5-mu-m Bi-CMOS process are proposed. It was shown that the minimum W(B) was limited by BV(CEO) and BV(EBO). The As-P emitter and SIC structures, annealed RTA, were found to be suitable for the advanced Bi-CMOS process.