A HIGH-SPEED, LOW-POWER DIVIDE-BY-4 FREQUENCY-DIVIDER IMPLEMENTED WITH ALINAS/GAINAS HBTS

被引：21

作者：

FARLEY, CW

WANG, KC

CHANG, MF

ASBECK, PM

NUBLING, RB

SHENG, NH

PIERSON, R

SULLIVAN, GJ

机构：

来源：

IEEE ELECTRON DEVICE LETTERS | 1989年 / 10卷 / 08期

关键词：

D O I：

10.1109/55.31762

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：377 / 379

页数：3

共 11 条

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IEEE TRANSACTIONS ON ELECTRON DEVICES, 1988, 35 (04) :401-404

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Mishra U. K., 1988, International Electron Devices Meeting. Technical Digest (IEEE Cat. No.88CH2528-8), P873, DOI 10.1109/IEDM.1988.32948

[8] ULTRA-HIGH-SPEED DIGITAL CIRCUIT PERFORMANCE IN 0.2-MU-M GATE-LENGTH ALINAS/GAINAS HEMT TECHNOLOGY [J].

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[10] A 20-GHZ FREQUENCY-DIVIDER IMPLEMENTED WITH HETEROJUNCTION BIPOLAR-TRANSISTORS [J].

WANG, KC ;

ASBECK, PM ;

CHANG, MF ;

SULLIVAN, GJ ;

MILLER, DL .

IEEE ELECTRON DEVICE LETTERS, 1987, 8 (09) :383-385

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