SYNCHRONOUS LOGIC SYNTHESIS - ALGORITHMS FOR CYCLE-TIME MINIMIZATION

被引：31
作者：
DEMICHELI, G
机构：
[1] Center for Integrated Systems, Computer Systems Laboratory, Stanford University, Stanford., CA
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1991年 / 10卷 / 01期
基金：
美国国家科学基金会;
关键词：
D O I：
10.1109/43.62792
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a new approach to logic synthesis of digital synchronous circuits. We present a model for synchronous circuits that supports logic transformations aimed at optimizing the circuit performance. Previous synthesis approaches attacked this problem by separating the combinational logic from the registers and by applying circuit transformations to the combinational component only. We show in this paper instead how to optimize concurrently the circuit equations and the register position by a set of algorithms based on logic transformations. Experimental results on benchmark circuits are reported. © 1991 IEEE
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页码：63 / 73
页数：11
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