EMULATION OF PROCESSOR FOR DISTRIBUTED PROCESSOR-MEMORY SYSTEM

被引:0
作者
MAUD, A [1 ]
PETERSON, JB [1 ]
机构
[1] USAF,INST TECHNOL,WRIGHT PATTERSON AFB,OH 45433
关键词
D O I
暂无
中图分类号
V [航空、航天];
学科分类号
08 ; 0825 ;
摘要
引用
收藏
页码:462 / 462
页数:1
相关论文
共 50 条
  • [21] TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory
    Park, Jaehyun
    Kim, Byeongho
    Yun, Sungmin
    Lee, Eojin
    Rhu, Minsoo
    Ahn, Jung Ho
    PROCEEDINGS OF 54TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2021, 2021, : 268 - 281
  • [22] MODELLING JITTER IN WIRELESS CHANNEL CREATED BY PROCESSOR-MEMORY ACTIVITY
    Yilmaz, Baki Berkay
    Zajic, Alenka
    Prvulovic, Milos
    2018 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP), 2018, : 2037 - 2041
  • [23] ASSIGNMENT OF TASKS IN A DISTRIBUTED PROCESSOR SYSTEM WITH LIMITED MEMORY
    RAO, GS
    STONE, HS
    HU, TC
    IEEE TRANSACTIONS ON COMPUTERS, 1979, 28 (04) : 291 - 299
  • [24] Randomizing Packet Memory Networks for Low-latency Processor-memory Communication
    Fujiki, Daichi
    Matsutani, Hiroki
    Koibuchi, Michihiro
    Amano, Hideharu
    2016 24TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP), 2016, : 168 - 175
  • [25] Designing Processor-Memory Interfaces with Monolithically Integrated Silicon-photonics
    Sun, Chen
    Chen, Yu-Hsin
    Stojanovic, Vladimir
    2013 CONFERENCE ON LASERS AND ELECTRO-OPTICS PACIFIC RIM (CLEO-PR), 2013,
  • [26] Predicting the performance of a 3D processor-memory chip stack
    Jacob, P
    Erdogan, O
    Zia, A
    Belemjian, PM
    Kraft, RP
    McDonald, JF
    IEEE DESIGN & TEST OF COMPUTERS, 2005, 22 (06): : 540 - 547
  • [27] Experimental Demonstration of Electromagnetic Information Leakage From Modern Processor-Memory Systems
    Zajic, Alenka
    Prvulovic, Milos
    IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2014, 56 (04) : 885 - 893
  • [28] A parallelized way to provide data encryption and integrity checking on a processor-memory bus
    Elbaz, Reouven
    Torres, Lionel
    Sassatelli, Gilles
    Guillemin, Pierre
    Bardouillet, Michel
    Martinez, Albert
    43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006, 2006, : 506 - +
  • [29] Processor-memory co-exploration driven by a memory-aware architecture description language
    Mishra, P
    Grun, P
    Dutt, N
    Nicolau, A
    VLSI DESIGN 2001: FOURTEENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, 2001, : 70 - 75
  • [30] Parallel Computing using Memristive Crossbar Networks: Nullifying the Processor-Memory Bottleneck
    Velasquez, Alvaro
    Jha, Sumit Kumar
    2014 9TH INTERNATIONAL DESIGN & TEST SYMPOSIUM (IDT), 2014, : 147 - 152